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MOTOROLA
Freescale Semiconductor, Inc.
SEMICONDUCTOR TECHNICAL DATA
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Advance Information
128K x 36 and 256K x 18 Bit Flow-Through BurstRAM Synchronous Fast Static RAM
The MCM63F737K and MCM63F819K are 4M-bit synchronous fast static RAMs designed to provide a burstable, high performance, secondary cache. The MCM63F737K (organized as 128K words by 36 bits) and the MCM63F819K (organized as 256K words by 18 bits) integrate input registers, a 2-bit address counter, and high speed SRAM onto a single monolithic circuit for reduced parts count in cache data RAM applications. Synchronous design allows precise cycle control with the use of an external clock (K). Addresses (SA), data inputs (DQx), and all control signals except output enable (G), sleep mode (ZZ), and linear burst order (LBO) are clock (K) controlled through positive-edge-triggered noninverting registers. Bursts can be initiated with either ADSP or ADSC input pins. Subsequent burst addresses can be generated internally by the MCM63F737K and MCM63F819K (burst sequence operates in linear or interleaved mode dependent upon the state of LBO) and controlled by the burst address advance (ADV) input pin. Write cycles are internally self-timed and are initiated by the rising edge of the clock (K) input. This feature eliminates complex off-chip write pulse generation and provides increased timing flexibility for incoming signals. Synchronous byte write (SBx), synchronous global write (SGW), and synchronous write enable (SW) are provided to allow writes to either individual bytes or to all bytes. The bytes are designated as "a", "b", etc. SBa controls DQa, SBb controls DQb, etc. Individual bytes are written if the selected byte writes SBx are asserted with SW. All bytes are written if either SGW is asserted or if all SBx and SW are asserted. For read cycles, a flow-through SRAM allows output data to simply flow freely from the memory array. The MCM63F737K and MCM63F819K operate from a 3.3 V core power supply and all outputs operate on a 2.5 V or 3.3 V power supply. All inputs and outputs are JEDEC standard JESD8-5 compatible. * MCM63F737K / MCM63F819K-8.5 = 8.5 ns Access MCM63F737K / MCM63F819K-9 ns = 9 ns Access MCM63F737K / MCM63F819K-11 ns = 11 ns Access * 3.3 V +10%, -5% Core Power Supply, 2.5 V or 3.3 V I/O Supply * ADSP, ADSC, and ADV Burst Control Pins * Selectable Burst Sequencing Order (Linear/Interleaved) * Single-Cycle Deselect Timing * Internally Self-Timed Write Cycle * Byte Write and Global Write Control * Sleep Mode (ZZ) * JEDEC Standard 100-Pin TQFP and 119-Pin PBGA Packages
MCM63F737K MCM63F819K
TQ PACKAGE TQFP CASE 983A-01
Freescale Semiconductor, Inc...
ZP PACKAGE PBGA CASE 999-02
This document contains information on a new product. Specifications and information herein are subject to change without notice.
10/1/99
(c) Motorola, Inc. 1999 MOTOROLA FAST SRAM
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MCM63F737K*MCM63F819K 1
Freescale Semiconductor, Inc.
FUNCTIONAL BLOCK DIAGRAM
LBO ADV K ADSC ADSP K2
BURST COUNTER CLR 2
2
17/18 128K x 36 / 256K x 18 ARRAY
SA SA1 SA0
ADDRESS REGISTER
17/18
15/16
SGW SW WRITE REGISTER a
36/18
36/18
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SBa
SBb
WRITE REGISTER b 4/2 WRITE REGISTER c* DATA-IN REGISTER K
SBc*
SBd*
WRITE REGISTER d*
K2
SE1 SE2 SE3 G ZZ * Valid only for MCM63F737K.
ENABLE REGISTER
DQa - DQd/ DQa - DQb
MCM63F737K*MCM63F819K 2
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Freescale Semiconductor, Inc.
MCM63F737K PIN ASSIGNMENTS
SA SA SE1 SE2 SBd SBc SBb SBa SE3 VDD VSS K SGW SW G ADSC ADSP ADV SA SA
1 DQb DQb DQb VDDQ VSS DQb DQb DQb DQb VSS VDDQ DQb DQb VSS NC VDD ZZ DQa DQa VDDQ VSS DQa DQa DQa DQa VSS VDDQ DQa DQa DQa A B C D E DQc F G DQc H J K L DQd M DQc VDDQ VDDQ NC NC DQc
2 SA SE2 SA DQc DQc DQc DQc DQc
3 SA SA SA VSS VSS VSS SBc VSS NC VSS SBd VSS VSS VSS LBO SA NC
4 ADSP ADSC VDD NC SE1 G ADV SGW VDD K NC SW SA1 SA0 VDD SA NC
5 SA SA SA VSS VSS VSS SBb VSS NC VSS SBa VSS VSS VSS NC SA NC
6
7
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DQc DQc DQc VDDQ VSS DQc DQc DQc DQc VSS VDDQ DQc DQc NC VDD NC VSS DQd DQd VDDQ VSS DQd DQd DQd DQd VSS VDDQ DQd DQd DQd
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 10 71 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 LBO SA SA SA SA SA1 SA0 NC NC VSS VDD NC NC SA SA SA SA SA SA SA
SA VDDQ SE3 SA DQb DQb NC NC DQb DQb
DQb VDDQ DQb DQb DQb DQb
VDDQ VDD DQd DQd DQd
VDD VDDQ DQa DQa DQa DQa
VDDQ DQd N P R T NC U VDDQ NC NC DQd DQd NC DQd DQd SA
DQa VDDQ DQa DQa SA NC NC DQa DQa NC ZZ VDDQ
100-PIN TQFP TOP VIEW
119-BUMP PBGA TOP VIEW Not to Scale
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MCM63F737K*MCM63F819K 3
Freescale Semiconductor, Inc.
MCM63F737K TQFP PIN DESCRIPTIONS
Pin Locations 85 Symbol ADSC Type Input Description Synchronous Address Status Controller: Active low, interrupts any ongoing burst and latches a new external address. Used to initiate a READ, WRITE, or chip deselect. Synchronous Address Status Processor: Active low, interrupts any ongoing burst and latches a new external address. Used to initiate a new READ, WRITE, or chip deselect (exception -- chip deselect does not occur when ADSP is asserted and SE1 is high). Synchronous Address Advance: Increments address count in accordance with counter type selected (linear/interleaved). Synchronous Data I/O: "x" refers to the byte being read or written (byte a, b, c, d).
84
ADSP
Input
83 (a) 51, 52, 53, 56, 57, 58, 59, 62, 63 (b) 68, 69, 72, 73, 74, 75, 78, 79, 80 (c) 1, 2, 3, 6, 7, 8, 9, 12, 13 (d) 18, 19, 22, 23, 24, 25, 28, 29, 30 86
ADV DQx
Input I/O
G
Input
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Asynchronous Output Enable Input: Low -- enables output buffers (DQx pins). High -- DQx pins are high impedance. Clock: This signal registers the address, data in, and all control signals except G, LBO, and ZZ. Linear Burst Order Input: This pin must remain in steady state (this signal not registered or latched). It must be tied high or low. Low -- linear burst counter. High -- interleaved burst counter. Synchronous Address Inputs: These inputs are registered and must meet setup and hold times. Synchronous Address Inputs: These pins must be wired to the two LSBs of the address bus for proper burst operation. These inputs are registered and must meet setup and hold times. Synchronous Byte Write Inputs: "x" refers to the byte being written (byte a, b, c, d). SGW overrides SBx. Synchronous Chip Enable: Active low to enable chip. Negated high -- blocks ADSP or deselects chip when ADSC is asserted. Synchronous Chip Enable: Active high for depth expansion. Synchronous Chip Enable: Active low for depth expansion. Synchronous Global Write: This signal writes all bytes regardless of the status of the SBx and SW signals. If only byte write signals SBx are being used, tie this pin high. Synchronous Write: This signal writes only those bytes that have been selected using the byte write SBx pins. If only byte write signals SBx are being used, tie this pin low. Sleep Mode: This active high asynchronous signal places the RAM into the lowest power mode. The ZZ pin disables the RAMs internal clock when placed in this mode. When ZZ is negated, the RAM remains in low power mode until it is commanded to READ or WRITE. Data integrity is maintained upon returning to normal operation. Core Power Supply. I/O Power Supply. Ground. No Connection: There is no connection to the chip.
89 31
K LBO
Input Input
32, 33, 34, 35, 44, 45, 46, 47, 48, 49, 50, 81, 82, 99, 100 36, 37
SA SA1, SA0
Input Input
93, 94, 95, 96 (a) (b) (c) (d) 98
SBx SE1
Input Input
97 92 88
SE2 SE3 SGW
Input Input Input
87
SW
Input
64
ZZ
Input
15, 41, 65, 91 4, 11, 20, 27, 54, 61, 70, 77 5, 10, 17, 21, 26, 40, 55, 60, 67, 71, 76, 90 14, 16, 38, 39, 42, 43, 66
VDD VDDQ VSS NC
Supply Supply Supply --
MCM63F737K*MCM63F819K 4
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MCM63F737K PBGA PIN DESCRIPTIONS
Pin Locations 4B Symbol ADSC Type Input Description Synchronous Address Status Controller: Active low, interrupts any ongoing burst and latches a new external address. Used to initiate a READ, WRITE, or chip deselect. Synchronous Address Status Processor: Active low, interrupts any ongoing burst and latches a new external address. Used to initiate a new READ, WRITE, or chip deselect (exception -- chip deselect does not occur when ADSP is asserted and SE1 is high). Synchronous Address Advance: Increments address count in accordance with counter type selected (linear/interleaved). Synchronous Data I/O: "x" refers to the byte being read or written (byte a, b, c, d).
4A
ADSP
Input
4G (a) 6K, 7K, 6L, 7L, 6M, 6N, 7N, 6P, 7P (b) 6D, 7D, 6E, 7E, 6F, 6G, 7G, 6H, 7H (c) 1D, 2D, 1E, 2E, 2F, 1G, 2G, 1H, 2H (d) 1K, 2K, 1L, 2L, 2M, 1N, 2N, 1P, 2P 4F
ADV DQx
Input I/O
G
Input
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Asynchronous Output Enable Input: Low -- enables output buffers (DQx pins). High -- DQx pins are high impedance. Clock: This signal registers the address, data in, and all control signals except G, LBO, and ZZ. Linear Burst Order Input: This pin must remain in steady state (this signal not registered or latched). It must be tied high or low. Low -- linear burst counter. High -- interleaved burst counter. Synchronous Address Inputs: These inputs are registered and must meet setup and hold times. Synchronous Address Inputs: These pins must be wired to the two LSBs of the address bus for proper burst operation. These inputs are registered and must meet setup and hold times. Synchronous Byte Write Inputs: "x" refers to the byte being written (byte a, b, c, d). SGW overrides SBx. Synchronous Chip Enable: Active low to enable chip. Negated high -- blocks ADSP or deselects chip when ADSC is asserted. Synchronous Chip Enable: Active high for depth expansion. Synchronous Chip Enable: Active low for depth expansion. Synchronous Global Write: This signal writes all bytes regardless of the status of the SBx and SW signals. If only byte write signals SBx are being used, tie this pin high. Synchronous Write: This signal writes only those bytes that have been selected using the byte write SBx pins. If only byte write signals SBx are being used, tie this pin low. Sleep Mode: This active high asynchronous signal places the RAM into the lowest power mode. The ZZ pin disables the RAMs internal clock when placed in this mode. When ZZ is negated, the RAM remains in low power mode until it is commanded to READ or WRITE. Data integrity is maintained upon returning to normal operation. Core Power Supply. I/O Power Supply. Ground. No Connection: There is no connection to the chip.
4K 3R
K LBO
Input Input
2A, 3A, 5A, 6A, 3B, 5B, 2C, 3C, 5C, 6C, 2R, 6R, 3T, 4T, 5T 4N, 4P
SA SA1, SA0
Input Input
5L, 5G, 3G, 3L (a) (b) (c) (d) 4E
SBx SE1
Input Input
2B 6B 4H
SE2 SE3 SGW
Input Input Input
4M
SW
Input
7T
ZZ
Input
4C, 2J, 4J, 6J, 4R 1A, 7A, 1F, 7F, 1J, 7J, 1M, 7M, 1U, 7U 3D, 5D, 3E, 5E, 3F, 5F, 3H, 5H, 3K, 5K, 3M, 5M, 3N, 5N, 3P, 5P 1B, 7B, 1C, 7C, 4D, 3J, 5J, 4L, 1R, 5R, 7R, 1T, 2T, 6T, 2U, 3U, 4U, 5U, 6U
VDD VDDQ VSS NC
Supply Supply Supply --
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MCM63F737K*MCM63F819K 5
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MCM63F819K PIN ASSIGNMENTS
SA SA SE1 SE2 NC NC SBb SBa SE3 VDD VSS K SGW SW G ADSC ADSP ADV SA SA
1 SA NC NC VDDQ VSS NC DQa DQa DQa VSS VDDQ DQa DQa VSS NC VDD ZZ DQa DQa VDDQ VSS DQa DQa NC NC VSS VDDQ NC NC NC A B C D E NC F G NC H J K L DQb M DQb VDDQ VDDQ NC NC DQb
2 SA SE2 SA NC DQb NC DQb NC
3 SA SA SA VSS VSS VSS SBb VSS NC VSS VSS VSS VSS VSS LBO SA NC
4 ADSP ADSC VDD NC SE1 G ADV SGW VDD K NC SW SA1 SA0 VDD NC NC
5 SA SA SA VSS VSS VSS VSS VSS NC VSS SBa VSS VSS VSS NC SA NC
6
7
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NC NC NC VDDQ VSS NC NC DQb DQb VSS VDDQ DQb DQb NC VDD NC VSS DQb DQb VDDQ VSS DQb DQb DQb NC VSS VDDQ NC NC NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 10 71 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 LBO SA SA SA SA SA1 SA0 NC NC VSS VDD NC NC SA SA SA SA SA SA SA
SA VDDQ SE3 SA DQa NC NC NC NC DQa
DQa VDDQ NC DQa DQa NC
VDDQ VDD NC DQb NC
VDD VDDQ NC DQa NC DQa NC SA SA NC DQa NC VDDQ NC DQa NC ZZ VDDQ
VDDQ DQb N P R T NC U VDDQ NC SA DQb NC NC NC DQb SA
100-PIN TQFP TOP VIEW
119-BUMP PBGA TOP VIEW Not to Scale
MCM63F737K*MCM63F819K 6
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MCM63F819K TQFP PIN DESCRIPTIONS
Pin Locations 85 Symbol ADSC Type Input Description Synchronous Address Status Controller: Active low, interrupts any ongoing burst and latches a new external address. Used to initiate a READ, WRITE, or chip deselect. Synchronous Address Status Processor: Active low, interrupts any ongoing burst and latches a new external address. Used to initiate a new READ, WRITE, or chip deselect (exception -- chip deselect does not occur when ADSP is asserted and SE1 is high). Synchronous Address Advance: Increments address count in accordance with counter type selected (linear/interleaved). Synchronous Data I/O: "x" refers to the byte being read or written (byte a, b). Asynchronous Output Enable Input: Low -- enables output buffers (DQx pins). High -- DQx pins are high impedance. Clock: This signal registers the address, data in, and all control signals except G, LBO, and ZZ. Linear Burst Order Input: This pin must remain in steady state (this signal not registered or latched). It must be tied high or low. Low -- linear burst counter. High -- interleaved burst counter. Synchronous Address Inputs: These inputs are registered and must meet setup and hold times. Synchronous Address Inputs: These pins must be wired to the two LSBs of the address bus for proper burst operation. These inputs are registered and must meet setup and hold times. Synchronous Byte Write Inputs: "x" refers to the byte being written (byte a, b). SGW overrides SBx. Synchronous Global Write: This signal writes all bytes regardless of the status of the SBx and SW signals. If only byte write signals SBx are being used, tie this pin high. Synchronous Chip Enable: Active low to enable chip. Negated high -- blocks ADSP or deselects chip when ADSC is asserted. Synchronous Chip Enable: Active high for depth expansion. Synchronous Chip Enable: Active low for depth expansion. Synchronous Write: This signal writes only those bytes that have been selected using the byte write SBx pins. If only byte write signals SBx are being used, tie this pin low. Sleep Mode: This active high asynchronous signal places the RAM into the lowest power mode. The ZZ pin disables the RAMs internal clock when placed in this mode. When ZZ is negated, the RAM remains in low power mode until it is commanded to READ or WRITE. Data integrity is maintained upon returning to normal operation. Core Power Supply. I/O Power Supply. Ground. No Connection: There is no connection to the chip.
84
ADSP
Input
83 (a) 58, 59, 62, 63, 68, 69, 72, 73, 74 (b) 8, 9, 12, 13, 18, 19, 22, 23, 24 86
ADV DQx G
Input I/O Input
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89 31
K LBO
Input Input
32, 33, 34, 35, 44, 45, 46, 47, 48, 49, 50, 80, 81, 82, 99, 100 36, 37
SA SA1, SA0
Input Input
93, 94 (a) (b) 88
SBx SGW
Input Input
98
SE1
Input
97 92 87
SE2 SE3 SW
Input Input Input
64
ZZ
Input
15, 41, 65, 91 4, 11, 20, 27, 54, 61, 70, 77 5, 10, 17, 21, 26, 40, 55, 60, 67, 71, 76, 90 1, 2, 3, 6, 7, 14, 16, 25, 28, 29, 30, 38, 39, 42, 43, 51, 52, 53, 56, 57, 66, 75, 78, 79, 95, 96
VDD VDDQ VSS NC
Supply Supply Supply --
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MCM63F737K*MCM63F819K 7
Freescale Semiconductor, Inc.
MCM63F819K PBGA PIN DESCRIPTIONS
Pin Locations 4B Symbol ADSC Type Input Description Synchronous Address Status Controller: Active low, interrupts any ongoing burst and latches a new external address. Used to initiate a READ, WRITE, or chip deselect. Synchronous Address Status Processor: Active low, interrupts any ongoing burst and latches a new external address. Used to initiate a new READ, WRITE, or chip deselect (exception -- chip deselect does not occur when ADSP is asserted and SE1 is high). Synchronous Address Advance: Increments address count in accordance with counter type selected (linear/interleaved). Synchronous Data I/O: "x" refers to the byte being read or written (byte a, b). Asynchronous Output Enable Input: Low -- enables output buffers (DQx pins). High -- DQx pins are high impedance. Clock: This signal registers the address, data in, and all control signals except G, LBO, and ZZ. Linear Burst Order Input: This pin must remain in steady state (this signal not registered or latched). It must be tied high or low. Low -- linear burst counter. High -- interleaved burst counter. Synchronous Address Inputs: These inputs are registered and must meet setup and hold times. Synchronous Address Inputs: These pins must be wired to the two LSBs of the address bus for proper burst operation. These inputs are registered and must meet setup and hold times. Synchronous Byte Write Inputs: "x" refers to the byte being written (byte a, b). SGW overrides SBx. Synchronous Chip Enable: Active low to enable chip. Negated high -- blocks ADSP or deselects chip when ADSC is asserted. Synchronous Chip Enable: Active high for depth expansion. Synchronous Chip Enable: Active low for depth expansion. Synchronous Global Write: This signal writes all bytes regardless of the status of the SBx and SW signals. If only byte write signals SBx are being used, tie this pin high. Synchronous Write: This signal writes only those bytes that have been selected using the byte write SBx pins. If only byte write signals SBx are being used, tie this pin low. Sleep Mode: This active high asynchronous signal places the RAM into the lowest power mode. The ZZ pin disables the RAMs internal clock when placed in this mode. When ZZ is negated, the RAM remains in low power mode until it is commanded to READ or WRITE. Data integrity is maintained upon returning to normal operation. Core Power Supply. I/O Power Supply. Ground. No Connection: There is no connection to the chip.
4A
ADSP
Input
4G (a) 6D, 7E, 6F, 7G, 6H, 7K, 6L, 6N, 7P (b) 1D, 2E, 2G, 1H, 2K, 1L, 2M, 1N, 2P 4F
ADV DQx G
Input I/O Input
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4K 3R
K LBO
Input Input
2A, 3A, 5A, 6A, 3B, 5B, 2C, 3C, 5C, 6C, 2R, 6R, 2T, 3T, 5T, 6T 4N, 4P
SA SA1, SA0
Input Input
5L, 3G (a) (b) 4E
SBx SE1
Input Input
2B 6B 4H
SE2 SE3 SGW
Input Input Input
4M
SW
Input
7T
ZZ
Input
4C, 2J, 4J, 6J, 4R 1A, 7A, 1F, 7F, 1J, 7J, 1M, 7M, 1U, 7U 3D, 5D, 3E, 5E, 3F, 5F, 5G, 3H, 5H, 3K, 5K, 3L, 3M, 5M, 3N, 5N, 3P, 5P 1B, 7B, 1C, 7C, 2D, 4D, 7D, 1E, 6E, 2F, 1G, 6G, 2H, 7H, 3J, 5J, 1K, 6K, 2L, 4L, 7L, 6M, 2N, 7N, 1P, 6P, 1R, 5R, 7R, 1T, 4T, 2U, 3U, 4U, 5U, 6U
VDD VDDQ VSS NC
Supply Supply Supply --
MCM63F737K*MCM63F819K 8
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MOTOROLA FAST SRAM
Freescale Semiconductor, Inc.
TRUTH TABLE (See Notes 1 Through 5)
Next Cycle Deselect Deselect Deselect Deselect Deselect Begin Read Begin Read Continue Read Continue Read Continue Read Continue Read Suspend Read Address Used None None None None None External External Next Next Next Next Current Current Current Current External Next Next Current Current SE1 1 0 0 X X 0 0 X X 1 1 X X 1 1 0 X 1 X 1 SE2 X X 0 X 0 1 1 X X X X X X X X 1 X X X X SE3 X 1 X 1 X 0 0 X X X X X X X X 0 X X X X ADSP X 0 0 1 1 0 1 1 1 X X 1 1 X X 1 1 X 1 X ADSC 0 X X 0 0 X 0 1 1 1 1 1 1 1 1 0 1 1 1 1 ADV X X X X X X X 0 0 0 0 1 1 1 1 X 0 0 1 1 G3 X X X X X 0 0 1 0 1 0 1 0 1 0 X X X X X DQx High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z DQ High-Z DQ High-Z DQ High-Z DQ High-Z High-Z High-Z High-Z High-Z Write 2, 4 X X X X X X READ READ READ READ READ READ READ READ READ WRITE WRITE WRITE WRITE WRITE
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Suspend Read Suspend Read Suspend Read Begin Write Continue Write Continue Write Suspend Write Suspend Write
NOTES: 1. X = don't care. 1 = logic high. 0 = logic low. 2. Write is defined as either 1) any SBx and SW low or 2) SGW is low. 3. G is an asynchronous signal and is not sampled by the clock K. G drives the bus immediately (tGLQX) following G going low. 4. On write cycles that follow read cycles, G must be negated prior to the start of the write cycle to ensure proper write data setup times. G must also remain negated at the completion of the write cycle to ensure proper write data hold times.
ASYNCHRONOUS TRUTH TABLE
Operation Read Read Write Deselected Sleep ZZ L L L L H G L H X X X I/O Status Data Out (DQx) High-Z High-Z High-Z High-Z
LINEAR BURST ADDRESS TABLE (LBO = VSS)
1st Address (External) X . . . X00 X . . . X01 X . . . X10 X . . . X11 2nd Address (Internal) X . . . X01 X . . . X10 X . . . X11 X . . . X00 3rd Address (Internal) X . . . X10 X . . . X11 X . . . X00 X . . . X01 4th Address (Internal) X . . . X11 X . . . X00 X . . . X01 X . . . X10
INTERLEAVED BURST ADDRESS TABLE (LBO = VDD)
1st Address (External) X . . . X00 X . . . X01 X . . . X10 X . . . X11 2nd Address (Internal) X . . . X01 X . . . X00 X . . . X11 X . . . X10 3rd Address (Internal) X . . . X10 X . . . X11 X . . . X00 X . . . X01 4th Address (Internal) X . . . X11 X . . . X10 X . . . X01 X . . . X00
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MCM63F737K*MCM63F819K 9
Freescale Semiconductor, Inc.
WRITE TRUTH TABLE
Cycle Type Read Read Write Byte a Write Byte b Write Byte c (See Note 1) Write Byte d (See Note 1) Write All Bytes Write All Bytes NOTE: 1. Valid Only for MCM63F737K. SGW H H H H H H H L SW H L L L L L L X SBa X H L H H H L X SBb X H H L H H L X SBc (See Note 1) X H H H L H L X SBd (See Note 1) X H H H H L L X
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ABSOLUTE MAXIMUM RATINGS (See Note 1)
Rating Power Supply Voltage I/O Supply Voltage Input Voltage Relative to VSS for Any Pin Except VDD Input Voltage (Three-State I/O) Output Current (per I/O) Package Power Dissipation Temperature Under Bias Storage Temperature Symbol VDD VDDQ Vin, Vout VIT Iout PD Tbias Tstg Value VSS - 0.5 to 4.6 VSS - 0.5 to VDD VSS - 0.5 to VDD + 0.5 VSS - 0.5 to VDDQ + 0.5 20 1.6 -10 to 85 -55 to 125 Unit V V V V mA W C C 2 Notes This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit.
NOTES: 1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability. 2. Power dissipation capability is dependent upon package characteristics and use environment. See Package Thermal Characteristics.
PACKAGE THERMAL CHARACTERISTICS
Rating Symbol Max Unit Notes
TQFP
Junction to Ambient (@ 200 lfm) Junction to Board (Bottom) Junction to Case (Top) Single-Layer Board Four-Layer Board RJA RJB RJC 40 25 17 9 C/W C/W C/W 1, 2 3 4
PBGA
Junction to Ambient (@ 200 lfm) Junction to Board (Bottom) Junction to Case (Top) Single-Layer Board Four-Layer Board RJA RJB RJC 38 22 14 5 C/W C/W C/W 1, 2 3 4
NOTES: 1. Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, board population, and board thermal resistance. 2. Per SEMI G38-87. 3. Indicates the average thermal resistance between the die and the printed circuit board. 4. Indicates the average thermal resistance between the die and the case top surface via the cold plate method (MIL SPEC-883 Method 1012.1).
MCM63F737K*MCM63F819K 10
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MOTOROLA FAST SRAM
Freescale Semiconductor, Inc.
DC OPERATING CONDITIONS AND CHARACTERISTICS
(VDD = 3.3 V +10%, -5%, TA = 0 to 70C, Unless Otherwise Noted) RECOMMENDED OPERATING CONDITIONS AND DC CHARACTERISTICS (Voltages Referenced to VSS = 0 V)
Parameter Symbol Min Typ Max Unit
2.5 V I/O SUPPLY
Supply Voltage I/O Supply Voltage Input Low Voltage Input High Voltage Input High Voltage I/O Pins Output Low Voltage (IOL = 2 mA) Output High Voltage (IOH = -2 mA) VDD VDDQ VIL VIH VIH2 VOL VOH 3.135 2.375 -0.3 1.7 1.7 -- 1.7 3.3 2.5 -- -- -- -- -- 3.6 2.9 0.7 VDD + 0.3 VDDQ + 0.3 0.7 -- V V V V V V V
3.3 V I/O SUPPLY
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Supply Voltage I/O Supply Voltage Input Low Voltage Input High Voltage Input High Voltage I/O Pins Output Low Voltage (IOL = 8 mA) Output High Voltage (IOH = -4 mA)
VDD VDDQ VIL VIH VIH2 VOL VOH
3.135 3.135 -0.5 2 2 -- 2.4
3.3 3.3 -- -- -- -- --
3.6 VDD 0.8 VDD + 0.5 VDDQ + 0.5 0.4 --
V V V V V V V
VIH
VSS
VSS - 1.0 V
20% tKHKH
Figure 1. Undershoot Voltage
MOTOROLA FAST SRAM
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MCM63F737K*MCM63F819K 11
Freescale Semiconductor, Inc.
SUPPLY CURRENTS
Parameter Input Leakage Current (0 V Vin VDD) Output Leakage Current (0 V Vin VDDQ) AC Supply Current (Device Selected, All Outputs Open, Freq = Max) Includes VDD Only MCM63F737K / 819K-8.5 MCM63F737K / 819K-9 MCM63F737K / 819K-11 Symbol Ilkg(I) Ilkg(O) IDDA Min -- -- -- Typ -- -- -- Max 1 1 395/330 370/300 350/285 30 15 Unit A A mA 2, 3, 4 Notes 1
CMOS Standby Supply Current (Device Deselected, Freq = 0, VDD = Max, All Inputs Static at CMOS Levels) Sleep Mode Supply Current (Device Deselected, Freq = Max, VDD = Max, All Other Inputs Static at CMOS Levels, ZZ VDD -0.2 V) TTL Standby Supply Current (Device Deselected, Freq = 0, VDD = Max, All Inputs Static at TTL Levels)
ISB2 IZZ
-- --
-- --
mA mA
5, 6 1, 5, 6
ISB3 ISB4
-- --
-- --
35 130/120 115/100 110/95 50/40 45/35 35/30
mA mA
5, 7 5, 6
Freescale Semiconductor, Inc...
Clock Running (Device Deselected, Freq = Max, VDD = Max, All Inputs Toggling at CMOS Levels) Static Clock Running (Device Deselected, Freq = Max, VDD = Max, All Inputs Static at TTL Levels)
MCM63F737K / 819K-8.5 MCM63F737K / 819K-9 MCM63F737K / 819K-11 MCM63F737K / 819K-8.5 MCM63F737K / 819K-9 MCM63F737K / 819K-11
ISB5
--
--
mA
5, 7
NOTES: 1. LBO and ZZ pins have an internal pull-up and pull-down, respectively; and will exhibit leakage currents of 5 A. 2. Reference AC Operating Conditions and Characteristics for input and timing. 3. All addresses transition simultaneously low (LSB) then high (MSB). 4. Data states are all zero. 5. Device is deselected as defined by the Truth Table. 6. CMOS levels for I/Os are VIT VSS + 0.2 V or VDDQ - 0.2 V. CMOS levels for other inputs are Vin VSS + 0.2 V or VDD - 0.2 V. 7. TTL levels for I/Os are VIT VIL or VIH2. TTL levels for other inputs are Vin VIL or VIH.
CAPACITANCE (f = 1.0 MHz, TA = 0 to 70C, Periodically Sampled Rather Than 100% Tested)
Parameter Input Capacitance Input/Output Capacitance Symbol Cin CI/O Min -- -- Typ 4 7 Max 5 8 Unit pF pF
MCM63F737K*MCM63F819K 12
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MOTOROLA FAST SRAM
Freescale Semiconductor, Inc.
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VDD = 3.3 V +10%, -5%, TA = 0 to 70C, Unless Otherwise Noted)
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . 1.0 V/ns (20% to 80%) Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V Output Load . . . . . . . . . . . . . . See Figure 2 Unless Otherwise Noted
READ/WRITE CYCLE TIMING (See Notes 1 and 2)
MCM63F737K-8.5 MCM63F819K-8.5 Parameter P Cycle Time Clock High Pulse Width Clock Low Pulse Width Clock Access Time Symbol S bl tKHKH tKHKL tKLKH tKHQV tGLQV tKHQX1 tKHQX2 tGLQX tGHQZ tKHQZ tADKH tADSKH tDVKH tWVKH tEVKH tKHAX tKHADSX tKHDX tKHWX tKHEX Min 11 4.5 4.5 -- -- 0 2 0 -- 2 2.0 Max -- -- -- 8.5 3.5 -- -- -- 3.5 3.5 -- MCM63F737K-9 MCM63F819K-9 Min 13.3 5.3 5.3 -- -- 0 2 0 -- 2 2.0 Max -- -- -- 9 3.5 -- -- -- 3.5 3.5 -- MCM63F737K-11 MCM63F819K-11 Min 15 6 6 -- -- 0 2 0 -- 2 2.0 Max -- -- -- 11 3.5 -- -- -- 3.5 3.5 -- Unit Ui ns ns ns ns ns ns ns ns ns ns ns 3, 4, 5 3, 4 3, 4 3, 4 3, 4, 5 Notes N
Freescale Semiconductor, Inc...
Output Enable to Output Valid Clock High to Output Active Clock High to Output Change Output Enable to Output Active Output Disable to Q High-Z Clock High to Q High-Z Setup Times: Address ADSP, ADSC, ADV Data In Write Chip Enable Address ADSP, ADSC, ADV Data In Write Chip Enable
Hold Times:
0.5
--
0.5
--
0.5
--
ns
NOTES: 1. Write is defined as either any SBx and SW low or SGW is low. Chip Enable is defined as SE1 low, SE2 high, and SE3 low whenever ADSP or ADSC is asserted. 2. All read and write cycle timings are referenced from K or G. 3. Measured at 200 mV from steady state. 4. This parameter is sampled and not 100% tested. 5. At any given voltage and temperature, tKHQZ max is less than tKHQX1 min for a given device and from device to device.
OUTPUT Z0 = 50 RL = 50 1.5 V
Figure 2. AC Test Load
MOTOROLA FAST SRAM
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MCM63F737K*MCM63F819K 13
Freescale Semiconductor, Inc.
2400 2200 CLOCK ACCESS TIME DELAY (ps) 2000 1800 1600 1400 1200 1000 800 600 400 200 0 0 20 40 60 80 100 LUMPED CAPACITANCE, CL (pF)
OUTPUT CL
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Figure 3. Lumped Capacitive Load and Typical Derating Curve
OUTPUT LOAD
OUTPUT BUFFER
TEST POINT
UNLOADED RISE AND FALL TIME MEASUREMENT INPUT WAVEFORM 2.4 0.6 2.4 0.6
OUTPUT WAVEFORM
2.4 0.6 tf
2.4 0.6
tr NOTES: 1. Input waveform has a slew rate of 1 V/ns. 2. Rise time is measured from 0.6 to 2.4 V unloaded. 3. Fall time is measured from 2.4 to 0.6 V unloaded.
Figure 4. Unloaded Rise and Fall Time Characterization
MCM63F737K*MCM63F819K 14
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MOTOROLA FAST SRAM
Freescale Semiconductor, Inc...
READ/WRITE CYCLES
tKHKL tKLKH
tKHKH
K
MOTOROLA FAST SRAM
B C D tKHQV BURST WRAPS AROUND tGLQV Q(A) tKHQX1 tKHQX2 Q(B) Q(B+1) Q(B+2) Q(B+3) tGHQZ Q(B) ADSP, SA SE2, SE3 IGNORED BURST READ BURST WRITE D(C) D(C+1) D(C+2) D(C+3) tGLQX Q(D) SINGLE READ
SA
A
ADSP
ADSC
ADV
SE1
E
Freescale Semiconductor, Inc.
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W
G
DQx
Q(n)
tKHQZ
DESELECTED
SINGLE READ
MCM63F737K*MCM63F819K 15
NOTE: E low = SE2 high and SE3 low. W low = SGW low and/or SW and SBx low.
EEEEEEEEEEEEE EEEEEEEEEEEEE EEEEEEEEEEEEE EEEEEEEEEEEEE EEEEEEEEEEEEE EEEEEEEEEEEEE
tZZS tZZQZ
Freescale Semiconductor, Inc...
EEEEEEEEEEEEEEEEEEEEEEEEEEE EEEEEEEEEEEEEEEEEEEEEEEEEEE EEEEEEEEEEEEEEEEEEEEEEEEEEE EEEEEEEEEEEEEEEEEEEEEEEEEEE EEEEEEEEEEEEEEEEEEEEEEEEEEE EEEEEEEEEEEEEEEEEEEEEEEEEEE EEEEEEEEEEEEEEEEEEEEEEEEEEE EEEEEEEEEEEEEEEEEEEEEEEEEEE EEEEEEEEEEEEEEEEEEEEEEEEEEE EEEEEEEEEEEEEEEEEEEEEEEEEEE EEEEEEEEEEEEEEEEEEEEEEEEEEE
I ZZ tZZREC
MCM63F737K*MCM63F819K 16
K ADS ADDR NORMAL OPERATION NO NEW READS OR WRITES ALLOWED
Freescale Semiconductor, Inc.
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ADV DQ ZZ W G E
MOTOROLA FAST SRAM
IDD NOTE: ADS low = ADSC low or ADSP low. ADS high = both ADSC, ADSP high. E low = SE1 low, SE2 high, SE3 low. IZZ (max) specifications will not be met if inputs toggle.
SLEEP MODE TIMING
IN SLEEP MODE NO READS OR WRITES ALLOWED NORMAL OPERATION
Freescale Semiconductor, Inc.
APPLICATION INFORMATION
SLEEP MODE A sleep mode feature, the ZZ pin, has been implemented on the MCM63F737K and MCM63F819K. It allows the system designer to place the RAM in the lowest possible power condition by asserting ZZ. The Sleep Mode Timing diagram shows the different modes of operation: Normal Operation, No READ/WRITE Allowed, and Sleep Mode. Each mode has its own set of constraints and conditions that are allowed. Normal Operation: All inputs must meet setup and hold times prior to sleep and t ZZREC nanoseconds after recovering from sleep. Clock (K) must also meet cycle, high, and low times during these periods. Two cycles prior to sleep, initiation of either a read or write operation is not allowed. No READ/WRITE: During the period of time just prior to sleep and during recovery from sleep, the assertion of either ADSC, ADSP, or any write signal is not allowed. If a write operation occurs during these periods, the memory array may be corrupted. Validity of data out from the RAM can not be guaranteed immediately after ZZ is asserted (prior to being in sleep). Sleep Mode: The RAM automatically deselects itself. The RAM disconnects its internal clock buffer. The external clock may continue to run without impacting the RAMs sleep current (IZZ). All inputs are allowed to toggle -- the RAM will not be selected and perform any reads or writes. However, if inputs toggle, the IZZ (max) specification will not be met. Note: It is invalid to go from stop clock mode directly into sleep mode. NON-BURST SYNCHRONOUS OPERATION Although this BurstRAM has been designed for high end MPU-based systems, these SRAMs can be used in other high speed memory applications that do not require the burst address feature. Most L2 caches designed with a synchronous interface can make use of the MCM63F737K and MCM63F819K. The burst counter feature of the BurstRAM can be disabled, and the SRAM can be configured to act upon a continuous stream of addresses. See Figure 5. CONTROL PIN TIE VALUES EXAMPLE (H VIH, L VIL)
Non-Burst Sync Non-Burst, Flow-Through SRAM ADSP H ADSC L ADV H SE1 L SE2 H LBO X
Freescale Semiconductor, Inc...
NOTE: Although X is specified in the table as a don't care, the pin must be tied either high or low.
K
ADDR
A
B
C
D
E
F
G
H
SE3
W
G
DQ
Q(A)
Q(B)
Q(C)
Q(D)
D(E)
D(F)
D(G)
D(H)
READS
WRITES
Figure 5. Example Configuration as Non-Burst Synchronous SRAM
MOTOROLA FAST SRAM
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MCM63F737K*MCM63F819K 17
Freescale Semiconductor, Inc.
ORDERING INFORMATION
(Order by Full Part Number) MCM
Motorola Memory Prefix Part Number
63F737K 63F819K XX
X
X
Blank = Trays, R = Tape and Reel Speed (8.5 = 8.5 ns, 9 = 9 ns, 11 = 11 ns) Package (TQ = TQFP, ZP = PBGA)
Full Part Numbers -- MCM63F737KTQ8.5 MCM63F737KTQ8.5R MCM63F737KZP8.5 MCM63F737KZP8.5R MCM63F819KTQ8.5 MCM63F819KTQ8.5R MCM63F819KZP8.5 MCM63F819KZP8.5R
MCM63F737KTQ9 MCM63F737KTQ9R MCM63F737KZP9 MCM63F737KZP9R MCM63F819KTQ9 MCM63F819KTQ9R MCM63F819KZP9 MCM63F819KZP9R
MCM63F737KTQ11 MCM63F737KTQ11R MCM63F737KZP11 MCM63F737KZP11R MCM63F819KTQ11 MCM63F819KTQ11R MCM63F819KZP11 MCM63F819KZP11R
Freescale Semiconductor, Inc...
MCM63F737K*MCM63F819K 18
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MOTOROLA FAST SRAM
Freescale Semiconductor, Inc.
PACKAGE DIMENSIONS
TQ PACKAGE TQFP CASE 983A-01
4X
e 0.20 (0.008) H A-B D
2X 30 TIPS
0.20 (0.008) C A-B D -D-
80 81 51 50
e/2
B E/2 B VIEW Y E1 E E1/2
BASE METAL PLATING
-A-
-B-
-X- X=A, B, OR D
b1 c
Freescale Semiconductor, Inc...
100 1 30
31
D1/2 D1 D
2X 20 TIPS
D/2
0.13 (0.005)
0.20 (0.008) C A-B D
A -H- -C-
SEATING PLANE
q
2
0.10 (0.004) C
q
3 VIEW AB
0.05 (0.002)
S
S
q
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE -H- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS -A-, -B- AND -D- TO BE DETERMINED AT DATUM PLANE -H-. 5. DIMENSIONS D AND E TO BE DETERMINED AT SEATING PLANE -C-. 6. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 (0.010) PER SIDE. DIMENSIONS D1 AND B1 DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -H-. 7. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE b DIMENSION TO EXCEED 0.45 (0.018). MILLIMETERS MIN MAX --- 1.60 0.05 0.15 1.35 1.45 0.22 0.38 0.22 0.33 0.09 0.20 0.09 0.16 22.00 BSC 20.00 BSC 16.00 BSC 14.00 BSC 0.65 BSC 0.45 0.75 1.00 REF 0.50 REF 0.20 --- 0.08 --- 0.08 0.20 0_ 7_ 0_ --- 11 _ 13 _ 11 _ 13 _ INCHES MIN MAX --- 0.063 0.002 0.006 0.053 0.057 0.009 0.015 0.009 0.013 0.004 0.008 0.004 0.006 0.866 BSC 0.787 BSC 0.630 BSC 0.551 BSC 0.026 BSC 0.018 0.030 0.039 REF 0.020 REF 0.008 --- 0.003 --- 0.003 0.008 0_ 7_ 0_ --- 11 _ 13 _ 11 _ 13 _
1 0.25 (0.010)
GAGE PLANE DIM A A1 A2 b b1 c c1 D D1 E E1 e L L1 L2 S R1 R2
q
A2
R2
A1
R1
L2 L L1 VIEW AB
q
1 2 q3
q q
MOTOROLA FAST SRAM
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MCM63F737K*MCM63F819K 19
EEEE CCCC EEEE CCCC
b
M
c1
C A-B
S
D
S
SECTION B-B
Freescale Semiconductor, Inc.
ZP PACKAGE 7 x 17 BUMP PBGA CASE 999-02
4X
0.20
119X
C
E
B
7 6 54 3 2 1 A B C D E F G H J K L M N P R T U
b 0.3 0.15
M M
ABC A
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. ALL DIMENSIONS IN MILLIMETERS. 3. DIMENSION b IS THE MAXIMUM SOLDER BALL DIAMETER MEASURED PARALLEL TO DATUM A. 4. DATUM A, THE SEATING PLANE, IS DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. DIM A A1 A2 A3 D D1 D2 E E1 E2 b e MILLIMETERS MIN MAX --- 2.40 0.50 0.70 1.30 1.70 0.80 1.00 22.00 BSC 20.32 BSC 19.40 19.60 14.00 BSC 7.62 BSC 11.90 12.10 0.60 0.90 1.27 BSC
D2
D
D1
16X
e
E2
6X
e E1 BOTTOM VIEW
Freescale Semiconductor, Inc...
TOP VIEW
0.25 A A3 0.35 A 0.20 A A A2 SIDE VIEW
SEATING PLANE
A1
A
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MCM63F737K*MCM63F819K For More Information On This Product, Go to: www.freescale.com 20
MOTOROLAMCM63F737K/D FAST SRAM

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